ARM TUTORIAL - 3

Data Processing Instructions
The general form for all Data Processing Instruction is shown below

• Each Instruction has a result register and 2 Operands.
• First Operand must be a register, but second can be a register or an immediate value.
• 32 bit shift is provided by barrel shifter which shifts the second operand by 32 bits within instruction cycle.
• S, SETS S flag. This affects CPSR.
  
  Data is manipulated within registers. Various instructions are-
  · Move Instructions
  · Arithmetic Instructions à Including Multiply Instructions
  · Logical Instructions
  · Comparison Instruction
  
  Suffix S on these Instruction updates flags in CPSR. Thus conditional flags will be set appropriately. (When S is not added flags will not be updated)
  
  1. MOVE INSTRUCTIONS
  MOV Rd,N
  --> Rd: Destination Register
  -->N : Immediate Value or source register
  --> Eg: MOV r7,r5
  
  MVN Rd,N
  --> Result in Rd will be NOT of 32 bit value of the source.
  
  MOV r7,r5,LSL#2 (Barrel Shifted)
  --> Multiplies the content in r5with 4 and puts the value in r7
  Ie, r7 <-- [r5]x4 2. ARITHEMETIC INSTRUCTIONS Simple Arithmetic Instructions implements 32 bit addition and subtraction. It employs 3 operands, 2 sources and a Destination. SUB r0,r1,r2 --> Subtract value stored in r2 from that of r1and store in r0.
  
  SUBS r1,r1,#1
  --> Subtract 1 from r1 and store result in r1 and update Z and C flags.
  
  Use of Barrel Shifter with Arithmetic and Logical Instructions increases the set of possible available operations.
  ADD r0,r1,r1 LSL #1
  --> Register r1 is shifted left by 1, (ie multiplied by 2), then it is added with r1 and the result is stored in r0.
  
  I. Multiply Instructions
  · Multiplies contents of a pair of registers.
  · Long Multiply generates 64 bit results.
  
  · MUL r0.r1,r2
  --> Contents of r1 and r2 are multiplied and the result is put in r0.
  
  · UMULL r0,r1,r2,r3
  --> Unsigned Multiply with results stored in r0 and r1. This is the case of a long unsigned multiplication.
  
  II. Multiply and Accumulate Instructions
  · Results of multiplication can be accumulated with the content of another register.
  
  · MLA Rd,Rm,Rs,Rn
  --> Rd= (Rm x Rs)+ Rn
  
  · UMLAL RdL,RdH,Rm,Rs
  --> [RdH,RdL]= [RdH,RdL]+(Rm+Rs)
  
  3. LOGICAL INSTRUCTIONS
  · Bit wise logical operation on 2 source registers.
  · Has 2 source registers and 1 destination register.
  · Operations possible- AND , OR, EX-OR, Bit Clear, ORR etc
  
  · AND r0,r1,r2 à r0=(r1&r2)
  
  · BIC r0,r1,r2 [ Bit Clear]
  --> r2 contains a binary pattern, where every binary 1 in r2 clears a corresponding bit location in r1.
  
  4. COMPARE INSTRUCTIONS
  Enables comparison of 32 bit value.
  Updates CPSR flags, but do not affect other registers.
  
  Simple Compare
  CMP r0,r9
  --> Flags sets as a result of r0-r9
  
  Test for Equality
  TEQ r0,r9
  --> Flags sets as a result of r0 EX-OR r9.
  
  Test
  TST r0,r9
  --> Flags sets as a result of r0 AND r9.
  
  Load and Store Instructions
  Transfers data between memory and processor registers. They are of 3 types-
  
• Single Register Transfer
• Multiple Register Transfer
• Swap Instructions
  
  1. SINGLE REGISTER TRANSFER
  Data types supported are signed and unsigned words (32 bits), half words, bytes.
  Load Instructions
  --> LDR – word (32 bits boundary)
  --> LDRH- Half word (16 bit boundary)
  --> LDRB- byte
  Store Instructions
  --> STR, STRH, STRB
  
  Eg:- LDR r0,[r1]
  
  2. MULTPLE REGISTER TRANSFER
  · Transfers Multiple Registers between memory and Processor in a single instruction.
  · More efficient for moving blocks and memory.
  · These instructions increase interrupt latency.
  · Mnemonics used are – LDM (Load), SDM (store)
  
  3. SWAP INSTRUCTIONS
  · Special case of Load and Store Instructions.
  · Instructions are-
  --> SWP: swap a word between memory and register
  --> SWPB: swap a byte.

Control Flow Instructions

• Branch and Conditional Branch
• Conditional Execution
• Branch and Link Instructions
• Subroutine return Instructions
  
  1. BRANCH AND CONDITIONAL BRANCH INSTRUCTIONS
  Branch Instruction has got 2 Variant
  Branch à B label : Eg- B forward
  Conditional Branch à B label: Eg- BNE loop (Conditions will be discussed later)
  
  2. CONDITIONAL EXECUITION
  Every instructions in ARM can be executed with respect to certain conditions.
  Eg : ADDEQ r0,r1,r2
  Advantages-
  · Reduces number of Branches
  · Increases Code density
  The table below shows various conditional codes, that can be added as suffix to all instructions in ARM.
  Condition Code Summary
  Eg :- ADDEQ r0,r1,r2
  This instruction will only be executed when zero flag is set.
  
  3. BRANCH AND LINK INSTRUCTIONS
  · Used for subroutine call.
  · While Branching, saves the address following the branch in link register.
  Eg- BL Subroutine
  
  4. SUBROUTINE RETURN INSTRUCTIONS
  · There are no specific instructions for RETURN from subroutine.
  · To return from subroutine, the value in link register has to be moved to Program counter, at the end of execution of subroutine.
  Eg- subroutine : --------------------
  --------------------
  MOV PC, r14
  
  Co-Processor Instructions
  Used to Extend Instruction set
  Instructions used
  CDP- Coprocessor Data processing
  LDC- Load Coprocessor from Memory
  
  These are the basics of ARM , especially ARM 7 processor. LPC 21XX, is on of the microcontroller build upon an ARM 7 TDMI core. Further details of LPC 21XX is available in its data sheet. I am concluding the Tutorial Series on the basics of ARM processor. Thank you for your cooperation.
  
  Link for LPC 21XX data sheet:-
  http://www.datasheetarchive.com/download/?url=http%3A%2F%2Fwww.datasheetarchive.com%2Fpdf%2FDatasheet-028%2FDSA00502688.pdf
  
  
  Happy Learning !!!!!!
  HARI
  haripanangad@yahoo.com
  http://www.haripanangad.co.cc/
  
  
  
  
  

ARM TUTORIAL 2

PROCESSOR MODES

• Processor Modes determines, which registers are active. They are used to define various kinds of registers, their visibility and rights to modify CPSR register.
• Each processor modes may be either- Privileged or Non-Privileged.
• Privileged Mode has full read write access to the CPSR.
• Non-Privileged Mode has only read access to control field CPSR, but read/write access to condition flags.

ARM has 7 different modes which come under Privileged and Non-privileged Modes. They are-

• Abort Mode
• Fast Interrupt Mode
• Interrupt Request Mode
• Supervisor Mode
• System Mode
• Undefined Mode
• User Mode

Abort Mode
Abort Mode is a mode, when there is a failed attempt to access memory.

Fast Interrupt request and Interrupt request Mode
These Corresponds to interrupt levels available on ARM. Fast Interrupt Request (FIQ) supports high speed interrupt handling. Interrupt Request (IRQ) supports, all other interrupt sources in a system.

Supervisor Mode
It is a state in which a processor goes after RESET. Generally, it is a mode in which OS Kernal executes. This is because, when a processor is RESET the first thing that it is expected to execute is its OS codes and not the user applications.

System Mode
Special Version of User Mode, that allows full read\write access to CPSR. It is also targeted for supervisory applications.

Undefined Mode
Processor Enters Undefined Mode when it encounters an undefined instruction. Eg:- illegal opcodes

User Mode
User Mode is used by program and applications. It is used to run the application codes. Once in user mode, the CPSR cannot be written to and modes can only be changed when an exception is generated.

Figure below shows Modes and Associated Registers

BANKED REGISTERS

• ARM has 37 registers in all.
• 20 registers are hidden from program at different times. These registers are called banked registers.
• Banked registers become available, when processor is in particular mode.
• The user registers R0-R7 are common to all operating modes.
• FIQ mode has its own R8-R14 that replace the user registers.
• Each of the other modes have their own R13 and R14.
• CPSR is common to all modes and there is an additional Saved program Status register (SPSR)

If processor goes to some other modes from user mode, example user mode to FIQ mode, FIQ has bank registers from R8 to R14. So effectively a fresh copy of R8 to R14 is made available in FIQ mode. When mode change takes place, content of CPSR will be saved to SPSR. When returned back, content of SPSR will be loaded back to CPSR.

ARM Memory organization and Data Types

• ARM can be configured as Little Endian or as Big Endian.

• Addresses are for each byte.
• Data word is 32 bit long.
• Word divided into 4 bytes of 8 bit each.
• Address is also 32 bit long.
• Addresses refers to byte ( Address 4 starts at byte 4)

ARM INSTRUCTION SET

• Instruction processes data in registers.
• Memory is accessed by load and store instructions.

Classes of instructions are-

• Data processing instructions
• Branch Instructions
• Load- Store instructions
• Software interrupt instructions
• Program Status Register Instructions
  
  The Instruction set will be discussed in next tutorial in detail.
  Happy learning !!!
  
  

ARM 7 TUTORIAL-1

ARM PROCESSOR OVERVIEW

ARM stands for Advanced RISC Machines. It is a 32 bit processor core, used for high end application.It is widely used in Advanced Robotic Applications. 

History and Development

• ARM was developed at Acron Computers ltd of Cambridge, England between 1983 and 1985.
• RISC concept was introduced in 1980 at Stanford and Berkley.
• ARM ltd was found in 1990.
• ARM cores are licensed to partners so as to develop and fabricate new microcontrollers around same processor cores.

ARM Architecture

• Architecture of ARM is Enhanced RISC Architecture.
• It has large uniform Register file.
• Employs Load Store Architecture- Here operations operate on registers and not in memory locations.
• Architecture is of uniform and fixed length.
• 32 bit processor. It also has 16 bit variant. ie it can be used as 32 bit and as 16 bit processor. 

Core Data path

An Architecture is characterized by Data path and control path.

• Data path is organized in such a way that, operands are not fetched directly from memory locations. Data items are placed in register files. No data processing takes place in memory locations.
• Instructions typically use 3 registers. 2 source registers and 1 destination register.
• Barrel Shifter preprocesses data, before it enters ALU.

à Barrel Shifter is basically a combinational logic circuit, which can shift data to left or right by arbitrary number of position in same cycle.

• Increment or Decrement logic can update register content for sequential access. 

ARM Organization

Register Bank is connected to ALU via two data paths.

• A bus
• B bus

B bus goes via Barrel Shifter. It preprocesses data from source register by shifting left or right or even rotating. The Program Counter is that part of register Bank , that generate address. Registers in register bank are symmetric ie, they can have both data and address. Program counter generates address for next  function.Address Incrementer block, increments or decrements register value independent of ALU. There is an Instruction Decode and control block, that provides control signals. (Not in figure) 

Pipeline

·         In ARM 7, a 3 stage pipeline is used. A 3 stage pipeline is the simplest form of pipeline that donot suffer from the problems such as read before write.

·         In a pipeline, when one instruction is executed, second instruction is decoded and third instruction will be fetched.

·         This is executed in a single cycle. 

Register Bank

• ARM 7 uses load and store Architecture.
• Data has to be moved from memory location to a central set of registers.
• Data processing is done and is stored back into memory.
• Register bank contains, general purpose registers to hold either data or address.
• It is a bank of 16 user registers R0-R15 and 2 status registers.
• Each of these registers are 32 bit wide. 

Data Registersà R0-R15

·         R0-R12à General Purpose Registers

·         R13-R15 à Special function registers of which,

R13à Stack Pointer, refers to entry pointer of Stack.

R14à Link Register, Return address is put to this when ever a subrou

tine is called.

R15à Program Counter

Depending upon application R13 and R14 can also be used as GPR. But not commonly used.In addition there are 2 status registers

• CPSRà Current program status register, status of current execution is stored.
• SPSRà Saved program Status register, includes status of program as well as processor.

CPSR

CPSR contains a number of flags which report and control the operation of ARM7 CPU.

Conditional Code Flags

Nà Negative Result from ALU

Zà Zero result from ALU

Cà ALU operation Carried out

Và ALU operation overflowed

Interrupt Enable Bits Ià IRQ, Interrupt Disable

FàFIQ, Disable Fast Interrupt

T- Bit

If

T=0, Processor in ARM Mode.

T=1, Processor in THUMB Mode

Mode Bits

Specifies the processor Modes. Processor Modes will be discussed in the next part of this tutorial. 

ARM features

• Barrel Shifter in data path that maximize the usage of hardware available on the chip.
• Auto increment and Auto decrement addressing modes to optimize program loop. This feature is not common in RISC architecture.
• Load and Store instruction to maximize data throughput.
• Conditional execution of instructions, to maximize execution throughput.

ARM Versions 

• Version 1 (1983-1985)

à 26 bit addressing

àNo multiply operation

àNo Co-processor 

• Version 2

à32 bit

à Includes result multiplication co-processor 

• Version 3

à 32 bit addressing 

• Version 4

à Added signed and unsigned operations 

• Version 4T (Thumb Mode)

à 16 bit thumb compressed mode of instruction introduced. Here given the same memory, if 16 bit instruction is used, additional instructions can be packed. Thus code density can be increased. Embedding a 16 bit variant in a 32 bit processor is called a THUMB. 

• Version 5T

à Superset of 4T adding new instructions. 

• Version 5TE

à Added DSP extension. 

Examples:-

ARM 6- Version 3

ARM 7- Version 3

ARM 7 TDMI- Version 4T (LPC21XX Series of Philips)

Strong ARM- Version 4 (intel)

ARM 9E-S- Version 5TE 

Happy Learning!!!!!!!!!!!   J

LARGE HADRON COLLIDER

The Large Hadron Collider (LHC) is a gigantic scientific instrument, which lies under France-Swiss border near Geneva, Switzerland. It is a particle accelerator used by physicists to study the smallest known particles which are said to be the fundamental building blocks of all things. It will surely change our understanding, from the minuscule world deep within atoms to the vastness of the Universe. The LHC was built by the European Organization for Nuclear Research (CERN), where scientists, engineers and support staffs from 111 nations are working together for one of the largest scientific experiment ever conducted.
The idea of LHC, began in early 1980s. It was initially approved in December 1994 by a council of CERN and the construction work began on April 1998. Initial Particle beam injections were successfully carried out on August 2008. In 10 september 2008 , the first attempt to circulate a beam through the entire LHC is being scheduled. The first high energy collisions are planned to take place after the LHC is officially unveiled, on 21 October 2008.

Lets just go through the gigantic instrument, The LHC. As its name suggests, it is a large collider of Hardons. An LHC basically consists of 3 major parts.

1) The Collider
2) The Detectors
3) The Grid

1) The Collider

Collider is one of the most essential parts of LHC. It is contained in a circular tunnel with a circumference of 27 Kilometers at a depth ranging from 50 to 175 meters underground at the Swiss-French border. The collider weighs more than 38000 tonnes. The collider tunnel contains two adjacent beam pipes which carries proton beams. The two beams will travel in opposite directions around the ring. There are about 1232 bending magnets and 392 focusing magnets installed within the pipes. Bending magnets keep beams on their circular path and focusing magnets are used to keep the beam focused. Approximately 96 tonnes of liquid helium is needed to keep the magnets at the operating temperature.

2) The Detectors

Particle detectors are simple in principle, but extremely complex in Practice. The detectors are built around the collision points where the particle beams meet head-on and they are designed to track the motion and measure the energy and charge of the new particles thrown out in all directions from the collisions. There are 6 detectors constructed at the LHC. They are ATLAS , Compact Muon Solenoid (CMS), A Large Ion Collider Experiment (ALICE), LHCb, TOTEM and LHCf.

Detectors are typically made up of layers. Each layer is designed to detect different properties of particles as they travel through the detector. The layers nearest to the collision point are designed precisely to track the movement of particles. These layers track the movement of the particles and also slow down and stop longer lived and more energetic particles. As these particles are slowed down they release energy which is measured by the calorimeters in these layers.

3) The Grid

Grid is said to be the successor of the Internet. Grid helps to share computer processing power, software packages and data storage space. It has many applications. Its major application will be to allow researchers at CERN to share global computing power to manage and process huge quantities of data that will be produced by the LHC.


Why LHC???

The LHC will allow scientists to go deeper into the heart of the matter and further back in time than has been possible using previous colliders. Universe is said to be originated in a Big Bang and since then the universe has been cooling down and becoming less energetic. The LHC will produce tiny patches of very high energy by colliding together atomic particles that are travelling in very high speed. The energy thus produced is very high than that existed during the evolution of the Universe.

Another interesting fact is that LHC will help to test the theories put forward by Prof Peter Higgs. Peters theory gives explanation for this –“ Different types of fundamental particles that make up matter have very different masses while particles that make up light have no mass at all”. When LHC is activated , the collider produces Higgs Boson, The verification of the existence of Higgs Boson will inturn help in search for Grand Unified Theory. Grand Unified Theory seeks to unify 3 of the 4 known fundamental forces- Electromagnetism, Strong Nuclear force and Weak Nuclear force. Gravity is the only force that is left out from the list. This Higgs Boson may also help to explain why gravitation is so weak compared to other forces.

The results from the LHC are not completely predictable as the experiments are testing ideas that are at the frontiers of our knowledge and understanding. Researchers expect to confirm predictions made on the basis of what we know from previous experiments and theories. However, part of the excitement of the LHC project is that it may uncover new facts about matter and the origins of the Universe.


How does LHC works???


The LHC accelerates two beams of atomic particles in opposite directions around the 27 km wide collider. When the particle beams reach their maximum speed the LHC allows them to ‘collide’ at 4 points on their circular journey. Thousands of new particles are produced when particles collide. With the help of detectors placed around the collision points, scientists could identify these new particles by tracking their behavior. As the energy produced in the collisions increases researchers are able to peer deeper into the fundamental structure of the Universe and further back into history. In these extreme conditions unknown atomic particles may appear.



Problems!!!!!

The high energy particle collision performed in LHC might produce dangerous phenomena including micro black holes, strangelets, Vacuum bubbles and magnetic monopoles.


Future

The LHC is still new, but its successor - the International Linear Collider (ILC) – is already being discussed. The LHC is a ‘discovery’ machine, a general purpose tool that will open up new areas of physics and demonstrate the existence, or not, of predicted new laws and particles. The ILC is a precision instrument that will allow scientists to explore in detail the discoveries made by the LHC.

The ILC is still at the planning stage, no location for the machine has been agreed and much feasibility testing has to be conducted before the construction phase.