Saturday, May 2, 2009



ARM stands for Advanced RISC Machines. It is a 32 bit processor core, used for high end application.It is widely used in Advanced Robotic Applications. 

History and Development

  • ARM was developed at Acron Computers ltd of Cambridge, England between 1983 and 1985.
  • RISC concept was introduced in 1980 at Stanford and Berkley.
  • ARM ltd was found in 1990.
  • ARM cores are licensed to partners so as to develop and fabricate new microcontrollers around same processor cores.

ARM Architecture

  • Architecture of ARM is Enhanced RISC Architecture.
  • It has large uniform Register file.
  • Employs Load Store Architecture- Here operations operate on registers and not in memory locations.
  • Architecture is of uniform and fixed length.
  • 32 bit processor. It also has 16 bit variant. ie it can be used as 32 bit and as 16 bit processor. 

Core Data path

An Architecture is characterized by Data path and control path.

  • Data path is organized in such a way that, operands are not fetched directly from memory locations. Data items are placed in register files. No data processing takes place in memory locations.
  • Instructions typically use 3 registers. 2 source registers and 1 destination register.
  • Barrel Shifter preprocesses data, before it enters ALU.

à Barrel Shifter is basically a combinational logic circuit, which can shift data to left or right by arbitrary number of position in same cycle.

  • Increment or Decrement logic can update register content for sequential access. 

ARM Organization

Register Bank is connected to ALU via two data paths.

  • A bus
  • B bus

B bus goes via Barrel Shifter. It preprocesses data from source register by shifting left or right or even rotating. The Program Counter is that part of register Bank , that generate address. Registers in register bank are symmetric ie, they can have both data and address. Program counter generates address for next  function.Address Incrementer block, increments or decrements register value independent of ALU. There is an Instruction Decode and control block, that provides control signals. (Not in figure) 


·         In ARM 7, a 3 stage pipeline is used. A 3 stage pipeline is the simplest form of pipeline that donot suffer from the problems such as read before write.

·         In a pipeline, when one instruction is executed, second instruction is decoded and third instruction will be fetched.

·         This is executed in a single cycle. 

Register Bank

  • ARM 7 uses load and store Architecture.
  • Data has to be moved from memory location to a central set of registers.
  • Data processing is done and is stored back into memory.
  • Register bank contains, general purpose registers to hold either data or address.
  • It is a bank of 16 user registers R0-R15 and 2 status registers.
  • Each of these registers are 32 bit wide. 

Data Registersà R0-R15

·         R0-R12à General Purpose Registers

·         R13-R15 à Special function registers of which,

R13à Stack Pointer, refers to entry pointer of Stack.

R14à Link Register, Return address is put to this when ever a subrou

tine is called.

R15à Program Counter

Depending upon application R13 and R14 can also be used as GPR. But not commonly used.In addition there are 2 status registers

  • CPSRà Current program status register, status of current execution is stored.
  • SPSRà Saved program Status register, includes status of program as well as processor.


CPSR contains a number of flags which report and control the operation of ARM7 CPU.

Conditional Code Flags

Nà Negative Result from ALU

Zà Zero result from ALU

Cà ALU operation Carried out

Và ALU operation overflowed

Interrupt Enable Bits Ià IRQ, Interrupt Disable

FàFIQ, Disable Fast Interrupt

T- Bit


T=0, Processor in ARM Mode.

T=1, Processor in THUMB Mode

Mode Bits

Specifies the processor Modes. Processor Modes will be discussed in the next part of this tutorial. 

ARM features

  • Barrel Shifter in data path that maximize the usage of hardware available on the chip.
  • Auto increment and Auto decrement addressing modes to optimize program loop. This feature is not common in RISC architecture.
  • Load and Store instruction to maximize data throughput.
  • Conditional execution of instructions, to maximize execution throughput.

ARM Versions 

  • Version 1 (1983-1985)

à 26 bit addressing

àNo multiply operation

àNo Co-processor 

  • Version 2

à32 bit

à Includes result multiplication co-processor 

  • Version 3

à 32 bit addressing 

  • Version 4

à Added signed and unsigned operations 

  • Version 4T (Thumb Mode)

à 16 bit thumb compressed mode of instruction introduced. Here given the same memory, if 16 bit instruction is used, additional instructions can be packed. Thus code density can be increased. Embedding a 16 bit variant in a 32 bit processor is called a THUMB. 

  • Version 5T

à Superset of 4T adding new instructions. 

  • Version 5TE

à Added DSP extension. 


ARM 6- Version 3

ARM 7- Version 3

ARM 7 TDMI- Version 4T (LPC21XX Series of Philips)

Strong ARM- Version 4 (intel)

ARM 9E-S- Version 5TE 

Happy Learning!!!!!!!!!!!   J